Technical Resources & Specifications

Technical specifications, CAD kernel benchmarks, dual-gate verification protocols, and manufacturing standard references for engineers and developers.

Working Spec — Revision 10 (September 2026)

The complete architectural specification defining Drawing Intelligence for Mid-Market Manufacturers. Details the harness-and-verify FLIP pipeline, the four honest verdict states, the key-first verification rule, and Features 1–13 spanning archive geometric retrieval, ASME Y14.5 conformance, change impact analysis, and drawing regeneration.

Working Spec Rev 10 Harness & Verify Features 1–13 Architecture Guide

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Ground-Truth Verification Benchmarks

Measured conversion benchmarks against known-good answer keys and professional solids. Evaluates IoU silhouette overlap, axis dimension matching, and torus fillet recognition across real factory prints.

EEI-3681 (93-98% IoU) Bracket Photo (16/16 Verified) Pump Cover (10/10 Matched) Bit-Identical STEP Cache

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Dual-Gate Referee Architecture

Deep dive into the referee layer: Size Gate matching stated values along principal axes, and Form Gate projecting silhouettes scored at 0.5 mm/px IoU with symmetric boundary deviation. How unstated features are catalogued.

Size Gate Form Gate Section Gate (Detail C) Silhouette Scoring

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Supported Standards & Ingest Formats

Implementation details for native 2D DWG and DXF vector extraction, multi-page PDF region segmentation, ASME Y14.5 feature control frame syntax, ISO GPS conformance, and downstream CAM STEP AP242 export.

ASME Y14.5 ISO GPS DWG / DXF Ingestion STEP AP242 B-Rep

Standards Reference →

Air-Gapped 72.7 MB Deployment Bundle

Technical guide for running Vertex and FLIP completely self-contained on factory networks. No external API dependencies, zero retention of proprietary geometry, and full ITAR-compliant operational isolation.

Air-Gapped Setup 72.7 MB Bundle (O170) Zero Network Transit Docker Container